The present invention relates in general to integrated circuit input/output (I/O) interfaces, and in particular to methods and circuitry for accurately phase shifting clock signals in a multiple-data-rate interface.
Various interfaces have been developed to increase data transfer rates and data throughput between integrated circuits. In a multiple-data-rate interface scheme, two or more bits of data are transferred during each clock period. A specific example is double-data-rate (DDR) technology, which performs two data operations in one clock cycle and achieves twice the data throughput. This technology has enhanced the bandwidth performance of integrated circuits used in a wide array of applications from computers to communication systems. The DDR technique is employed in, for example, synchronous dynamic random access memory (SDRAM) circuits.
DDR interfaces process I/O data (also referred to as DQ signals) using both the rising edge and falling edges of a clock signal DQS that functions as a data strobe to control the timing of data transfers. DQS is normally edge-aligned with DQ for a DDR interface operating in read mode (i.e., when receiving data at the DQS). For optimum data sampling, DQS is delayed by one-quarter of a clock period so that there is a 90 degree phase shift between the edges of DQ and DQS. This ensures that the DQS edge occurs close to the center of the DQ pulse. It is desirable to implement this 90 degree phase shift in a way that is as accurate and as stable as possible. But typical phase shift techniques that use, for example, delay chains, are highly susceptible to process, voltage, temperature, and other variations. In addition, typical DDR timing specifications require a wide frequency range of operation from, e.g., 133 MHz to 200 MHz. This places further, demands on the performance of the phase shift circuitry.
To ensure proper data transfer at multiple-data-rate interfaces, it is desirable to devise methods and apparatus for phase shifting clock signals in an accurate and stable manner.